The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Electrically programmable memory arrays (EPMAs) include memory cells. Each cell may include a resistive altering type material, such as a phase-change material, and have an associated HIGH or LOW state. The HIGH and LOW states are stored and associated with a logic one (1) or zero (0) data bit. Phase-change material has states that range from a fully amorphous state (less ordered state) to a fully crystalline state (more ordered state). As the phase-change material changes from the fully amorphous state to the fully crystalline state, the resistance of the phase-change material decreases.
Referring now to FIG. 1, a schematic view of an example EPMA 10 is shown and includes memory cells 12 that are arranged in rows and columns. Each row is asserted via a word line 14 and each column is asserted via a bit line 16. Each memory cell 12 includes a phase-change memory (PCM) element 18 and a switch 20. The PCM elements 18 include first and second ends 22, 24. The switch has gate, drain and source terminals 26, 28, 30. The gate terminals 26 are coupled to the word lines 14. The drain terminals 28 are coupled to the first ends 22. The source terminals 30 are coupled to ground 32. The second ends 24 are coupled to the bit lines 16.
Capacitance associated with each of the bit lines 16 varies depending upon resistive state of the unselected PCM elements 18. This variance in capacitance may be due to parasitic capacitance between the ends 22 and the drain terminals 28. Variance in the bit line capacitance can negatively affect the ability to accurately detect the state of a PCM element.
Referring now to FIGS. 2A and 2B, a cross-sectional side view and a top view of an EPMA 40 are shown. The top view shows a layout of word lines 42, bit lines 44, and PCM elements 46. The EPMA 40 includes multiple layers that are formed in three phases. The three phases are associated with the formation of base layers 50, a phase-change material layer 52 and upper metal layers 54.
During the first phase, the base layers 50 are formed in a first facility. A first insulating layer 60 is applied on a substrate layer 62. The first insulating layer 60 and the substrate layer 62 include switches 63 with corresponding gate, drain and source terminals 64, 66, 68. Contacts 70 are formed in the first insulating layer 60 for connection with the gate, drain and source terminals 64, 66, 68. The first facility has equipment that is capable of providing fine pitch geometries and thus high-density substrates. In other words, a large number of switches are formed per unit area of the substrate layer 62.
During the second phase, the base layers 50 are transported to a second facility to form the phase-change material layer 52. The transport of the base layers 50 to a second facility prevents contamination of first facility equipment due to formation of the phase-change material layer 52. The phase-change material layer 52 is formed on the first insulating layer 60. Photolithography is used to pattern the phase-change material layer 52 to create the PCM elements 46. Precise photolithography equipment is used to provide increased density of PCM elements. Photolithography equipment, in general, may have varying degrees of precision. Increased precision allows for increased memory array density, but has associated increased manufacturing costs.
During a third phase, the base layers 50 and the phase-change material layer 52 are returned to the first facility to form the upper metal layers 54. The upper metal layers 54 include a bit line layer 80 and a word line layer 82. A second insulating layer 86 is formed over the phase-change material layer 52 followed by the bit line layer 80. Electrical vias 88 are formed in the second-insulating layer 86 to provide contact to the gate and source terminals 64, 68 and the PCM elements 46. The bit line layer 80 is patterned to form bit lines 90 and electrical connections 92. The bit lines 90 are connected to the PCM elements 46, which are connected to the drain terminals 66 by the contacts 70. The electrical connections 92 are connected to the gate and source terminals 64, 68 by the contacts 70.
A third insulating layer 100 is formed over the bit line layer 80 followed by the word line layer 82. Electrical vias 102 are formed in the third insulating layer 100 to provide contact to the electrical connections 92. The word line layer 82 is also patterned to create the word lines 42.